訂閱電子報，掌握最新科技與產業趨勢
DESCRIPTION
The STM32WB55xx and STM32WB35xx multiprotocol wireless and ultra-low-power devices embed a powerful and ultra-low-power radio compliant with the Bluetooth® Low Energy SIG specification v5.0 and with IEEE 802.15.4-2011. They contain a dedicated Arm® Cortex® -M0+ for performing all the real-time low layer operation.
The devices are designed to be extremely low-power and are based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 64 MHz. The Cortex®-M4 core features a Floating point unit (FPU) single precision that supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) that enhances application security.
Enhanced inter-processor communication is provided by the IPCC with six bidirectional channels. The HSEM provides hardware semaphores used to share common resources between the two processors.
The devices embed high-speed memories (up to 1 Mbyte of Flash memory for STM32WB55xx, up to 512 Kbytes for STM32WB35xx, up to 256 Kbytes of SRAM for STM32WB55xx, 96 Kbytes for STM32WB35xx), a Quad-SPI Flash memory interface (available on all packages) and an extensive range of enhanced I/Os and peripherals.
FEATURES
- 2 independent cores for real time execution
- Ultra-low-power consumption
*STMicroelectronics Authorized Distributor
The STM32WB55xx and STM32WB35xx multiprotocol wireless and ultra-low-power devices embed a powerful and ultra-low-power radio compliant with the Bluetooth® Low Energy SIG specification v5.0 and with IEEE 802.15.4-2011. They contain a dedicated Arm® Cortex® -M0+ for performing all the real-time low layer operation.
The devices are designed to be extremely low-power and are based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 64 MHz. The Cortex®-M4 core features a Floating point unit (FPU) single precision that supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) that enhances application security.
Enhanced inter-processor communication is provided by the IPCC with six bidirectional channels. The HSEM provides hardware semaphores used to share common resources between the two processors.
The devices embed high-speed memories (up to 1 Mbyte of Flash memory for STM32WB55xx, up to 512 Kbytes for STM32WB35xx, up to 256 Kbytes of SRAM for STM32WB55xx, 96 Kbytes for STM32WB35xx), a Quad-SPI Flash memory interface (available on all packages) and an extensive range of enhanced I/Os and peripherals.
FEATURES
- 2 independent cores for real time execution
- Ultra-low-power consumption
- 50 μA/MHz Active mode (at 3.0V)
- 2.1 μA Stop mode (Radio in standby + 256KB RAM)
- < 50 nA Shutdown mode
- 2xI²C, 1xUSART, 1xLP-UART, 2xSPI, 1x USB 2.0 FS device supporting Battery Charging Detection, 1xSAI, Quad-SPI (XIP), 6x 16-bit timer (including LPWM and low-power one)- 1.7 to 3.6V voltage range (DC/DC, LDO)
*STMicroelectronics Authorized Distributor
