ECP5 / ECP5-5G
Costing 40% less than competing FPGAs, ECP5 and ECP5-5G provide connectivity to ASICs and ASSPs with improved routing architecture, dual channel SERDES, and enhanced DSP blocks for up to 4x improved multiplier utilization. Up to 85K LUTs in 10 x 10 mm, 0.5 mm pitch package with SERDES. Smart ball depopulation simplifies package integration with existing low cost PCB technology.
●Up to 3.2 Gbps SERDES rate with ECP5, and up to 5 Gbps with ECP5-5G
●Up to 4 channels per device in dual channel blocks for higher granularity
●Enhanced DSP blocks provide 2x resource improvement for symmetrical filters
●Single event upset (SEU) mitigation support
●Programmable IO support for LVCMOS 33/25/18/15/12, XGMII, LVTTL, LVDS, Bus-LVDS, 7:1 LVDS, LVPECL and MIPI D-PHY input interfaces

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