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Astera Labs
PCIe/CXL Smart Retimer
PT4161L, PT5161L
Astera Labs delivers industry-proven Smart Retimers that overcome signal integrity issues for PCI Express® (PCIe®) 4.0, PCIe 5.0, and Compute Express Link™ (CXL™) systems.
Aries Smart Retimers are purpose-built 100% in the cloud and for the cloud, offering extensive fleet management capabilities and tested for robust, seamless interoperation in their Cloud-Scale Interop Lab. As the #1 choice for CPU / GPU vendors and cloud operators, Aries is the industry’s most widely-deployed and field-tested PCIe / CXL Retimer portfolio.
PT4161L PCI Express® Gen-4 x16 Low-Latency Smart Retimer
The PT4161L is a 16-Lane PCI Express® (PCIe) Gen-4 protocol-aware low-latency Retimer designed to integrate seamlessly between a Root Complex and End Point(s) extending the reach by >28 dB at 16 GT/s. Compliant to all PCIe 4.0 rates and Retimer functional requirements, the PT4161L enables more system topologies and lower total solution cost while minimizing implementation overhead and Bill of Materials (BoM).
The innovative protocol-non-disruptive low-latency architecture of PT4161L significantly reduces latency through the Retimer while being transparent to system software and participating in Link Equalization with the Root Complex and End Point(s) to optimize Link performance. The PT4161L can autonomously dapt its latency to maximize performance during normal operational Link state (L0) while maintaining protocol interoperation.
To support a wide variety of End Points and port configurations, the PT4161L can bifurcate to one x16 Link, two x8 Links, four x4 Links, eight x2 Links, and more. Each Link operates independently, and per-Link diagnostics information such as Link state history and electrical margin are accessible through in-band (Receiver margining) and out-of-band (SMBus) methods.
The PT4161L uses a standard PCIe 100-MHz HCSL input clock and provides a 100-MHz HCSL output clock to drive other Retimer devices or PCIe components in the system.
The pinout is based on the Intel Retimer Supplemental Specification and uses an 8.9-mm x 22.8-mm Flip-Chip CSP package. The pinout allows for separate single-layer routing for all high-speed transmit and receive signals. Compact design, minimal supporting circuitry, and integrated AC-coupling capacitors greatly reduces overall solution size, making the PT4161L ideal for spacerestricted applications like system boards and riser cards.
Benefits and Features
- Compatible with PCIe Gen-4/3/2/1
- 16 GT/s, 8 GT/s, 5 GT/s, and 2.5 GT/s Data Rates with Automatic Link Equalization
- Low-Latency Mode Enables Cache-Coherent Links
- 16 Lanes with Flexible Link Bifurcation Including 1x16, 2x8, 4x4, 8x2, and Others
- Extends Reach by >28 dB at 16 GT/s Enabling LowCost PCB Materials and Connectors
- Receiver and Transmitter Performance Exceeds PCI Express® Base Specification Requirements
- No System Software Required • BGA Package Footprint Optimized for Board Routing
- Integrated AC-Coupling Capacitors Reduce Solution Size and Improves Signal Integrity Performance
- Supports SRIS, SRNS, and Common Clock Systems
- Supports Hot Plug and Hot Un-Plug • Supports Lane Margining at the Receiver for Both Timing and Voltage
- Supports Slave Loopback • Supports Systems with Lane Reversal and Implements Automatic Polarity Correction
- Low-Power Advanced CMOS Process
- HCSL Reference Clock Output Eliminates Clock Buffers to Drive Downstream PCIe Components
- Advanced In-Band and Out-of-Band Diagnostics for Fleet Management, Large-Scale Server Deployments
- Full-Featured C and Python SDKs for Rapid Integration of Advanced Diagnostics Features
- Device Configuration through SMBus or EEPROM
- IEEE 1149.6 AC-JTAG Boundary Scan
- Full Portfolio of Pin- and Register-Compatible Retimers Enables Easy Performance Scaling Up to PCI Express® Gen-5
Applications
-
Server and High-Performance PC Motherboards
-
PCIe Riser and Add-in Cards
-
Server-to-Server Cabled Interfaces
-
NVMe JBOFs, GPU/Deep-Learning Accelerators
PT5161L PCI Express® Gen-5 and Compute Express Link™ x16 Low-Latency Smart Retimer
The PT5161L is a 16-Lane PCI Express® (PCIe®) Gen-5 and Compute Express Link™ (CXL™) protocol-aware lowlatency Retimer designed to integrate seamlessly between a Root Complex and End Point(s) extending the reach by 36 dB at 32 GT/s. Compliant to all PCIe 5.0 rates and Retimer functional requirements, the PT5161L enables more system topologies and lower total solution cost while minimizing implementation overhead and Bill of Materials (BoM).
The innovative protocol-non-disruptive low-latency architecture of PT5161L significantly reduces latency through the Retimer while being transparent to system software and participating in Link Equalization with the Root Complex and End Point(s) to optimize Link performance. The PT5161L can autonomously adapt its latency to maximize performance during normal operational Link state (L0) while maintaining protocol interoperation.
To support a wide variety of End Points and port configurations, the PT5161L can bifurcate to one x16 Link, two x8 Links, four x4 Links, eight x2 Links, and more. Each Link operates independently, and per-Link diagnostics information such as Link state history and electrical margin are accessible through in-band (Receiver margining) and out-of-band (SMBus) methods.
The PT5161L uses a standard PCIe 100-MHz HCSL input clock and provides a 100-MHz HCSL output clock to drive other Retimer devices or PCIe components in the system. The pinout is based on the Intel Retimer Supplemental Specification and uses an 8.9-mm x 22.8-mm Flip-Chip CSP package. The pinout allows for separate single-layer routing for all high-speed transmit and receive signals. Compact design, minimal supporting circuitry, and integrated AC-coupling capacitors greatly reduces overall solution size, making the PT5161L ideal for spacerestricted applications like system boards and riser cards.
Benefit and Features
- Compatible with PCI Express® Gen-5/4/3/2/1 and Compute Express Link™
- 32 GT/s, 16 GT/s, 8 GT/s, 5 GT/s, and 2.5 GT/s Data Rates with Automatic Link Equalization
- Low-Latency Mode Enables Cache-Coherent Links
- 16 Lanes with Flexible Link Bifurcation Including 1x16, 2x8, 4x4, 8x2, and Others
- Extends Reach by >36 dB at 32 GT/s Enabling LowCost PCB Materials and Connectors
- Receiver and Transmitter Performance Exceeds PCIe® Base Specification Requirements
- No System Software Required
- BGA Package Footprint Optimized for Board Routing
- Integrated AC-Coupling Capacitors Reduce Solution Size and Improves Signal Integrity Performance
- Supports SRIS, SRNS, and Common Clock Systems
- Supports Hot Plug and Hot Un-Plug
- Supports Lane Margining at the Receiver for Both Timing and Voltage
- Supports Slave Loopback
- Supports Systems with Lane Reversal and Implements Automatic Polarity Correction
- HCSL Reference Clock Output Eliminates Clock Buffers to Drive Downstream PCIe Components
- Advanced In-Band and Out-of-Band Diagnostics for Fleet Management, Large-Scale Server Deployments
- Full-Featured C and Python SDKs for Rapid Integration of Advanced Diagnostics Features
- Device Configuration through SMBus or EEPROM
- IEEE 1149.6 AC-JTAG Boundary Scan
- Full Portfolio of Pin- and Register-Compatible Retimers Enables Easy Performance Scaling Between CXL and PCIe Gen-4 and Gen-5
Applications
- Server and High-Performance PC Motherboards
- PCIe Riser and Add-in Cards
- Server-to-Server Cabled Interfaces
- NVMe JBOFs, GPU/Deep-Learning Accelerators
Product Brochure
*Astera Labs Authorized Distributor
