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Astera Labs
2020/08/13

Astera Labs Announces Broad Availability of Aries Smart Retimers for PCIe® 4.0 and 5.0 Interconnects; Launches Cloud-Scale Interop Lab

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Astera Labs, a pioneer in connectivity solutions for intelligent systems, today announced that its Aries Smart Retimers designed to PCI Express® (PCIe®) 4.0 architecture (PT4161L) have entered mass production while Aries Smart Retimers designed to PCIe 5.0 architecture (PT5161L) are actively being sampled with strategic customers.

“Production release of PT4161L x16 PCIe 4.0 Smart Retimers and active sampling of pin-compatible PT5161L x16 PCIe 5.0 Smart Retimers is a critical milestone for the industry, clearing the way for wide deployment of PCIe solutions,” said Jitendra Mohan, CEO, Astera Labs. “Alongside our products, we are unveiling our Cloud-Scale Interop Lab service which provides the necessary testing infrastructure to our customers to ensure seamless interoperation and robust designs of their PCIe 4.0 and PCIe 5.0 systems.”

Aries Smart Retimers are the industry’s first pin compatible PCIe 4.0 and 5.0 retimer upgrade solution with successful deployment at multiple cloud and server OEMs, and interoperability testing alongside leading CPU, GPU and end point vendors. For further product and purchasing details, visit www.asteralabs.com/products-services/.

Supporting Quotes
“QCT understands that higher-bandwidth, lower-latency PCIe 5.0 and 4.0 interconnects are essential for cloud-optimized solutions to run specialized workloads, such as artificial intelligence and machine learning,” said Mike Yang, President, Quanta Cloud Technology (QCT). “QCT is leading the way to solve these next-generation datacenter design and operation challenges, and we are excited to partner with Astera Labs on purpose-built PCIe Smart Retimer solutions.”

“We are pleased to collaborate with Astera Labs using our industry-leading manufacturing techniques to deliver Aries Smart Retimers to market,” said Bradford Paulsen, Senior Vice President of Business Management, TSMC North America. “We look forward to quickly satisfying the massive customer demand for their cloud-optimized connectivity solutions.”

“PCIe 5.0 technology is critical to the next-gen device interconnect and acceleration of heterogenous compute architectures,” said Michael Hall, Director of Technology and Ecosystem Enabling at Intel. “Enterprise-class PCIe 4.0 and 5.0 retimer solutions that interoperate with Intel platforms, such as Astera Labs’ Aries Smart Retimers, are instrumental to the enablement of high-performance standard PCIe 5.0 interconnect across the entire ecosystem.”

“As a PCI-SIG® member, Astera Labs has been a contributor to the advancement of our specifications with its expertise of PCIe retimer technology,” said Al Yanes, PCI-SIG Chairman and President. “It is great to see Aries Smart Retimers broadly available to system developers, which will enable rapid PCIe 4.0 technology and PCIe 5.0 technology ecosystem expansion.”

Astera Labs Unveils New Cloud-Scale Interop Lab with Ecosystem Partners
Astera Labs has launched its Cloud-Scale Interop Lab as an ongoing collaboration with industry partners, so customers can design with confidence, reduce development time and trust that integration of Aries Smart Retimers will be seamless and straightforward.

Cloud-Scale Interop Lab Resources:
Supporting Quotes
“Samsung is driving storage performance boundaries with its PCIe 4.0 PM1733 and PM1735 SSD solutions, which deliver cutting-edge memory capabilities to address today’s enterprise data demands,” said Hangu Sohn, vice president of NAND Memory Planning, Samsung Electronics. “The Cloud-Scale Interop Lab from Astera Labs helps ensure seamless interoperability within the latest PCIe 4.0 systems and verifies that the resulting connection can handle the rigors of enterprise operation.”

“PCIe 4.0 technology can help remove storage performance bottlenecks for next-generation data center applications and use cases, and we’re excited to take part in Astera Labs’ Cloud-Scale Interop Lab to support Aries Smart Retimers for enterprise PCIe 4.0 system designers,” said Richard New, vice president of research, Western Digital.
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